In this Letter, we propose a 266–2133 MHz phase shifter using all-digital delay-locked loop (DLL) and phase interpolator (PI) that support training operations for LPDDR4X interface. The injection-locked oscillator (ILO)-based phase shifter is small in area and good linearity, but it is not suitable for applications with a wide frequency range due to its inherent narrow locking range characteristics . Although the phase shifter using a delay line (DL) achieves good power efficiency and linearity, it is difficult to perform 1UI-based phase shifting, and the power consumption will be increased at low frequencies . To improve the timing margin over a wide frequency range and increase the maximum achievable data-rate, however, the jitter and linearity of the phase shifter should be also enhanced.Ī PLL-based phase shifter can reduce jitter, but require a large number of clock (CLK) distribution lines in a multi-channel architecture, which consumes a lot of power and occupies a large area . Recently, various techniques such as C I/O minimisation and dual-loop phase-locked loop (PLL) have been introduced to increase data-rate of memory interface.
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